This application claims, under 35 U.S.C. xc2xa7119, the benefit of Korean Patent Application No. P2001-76687 filed on Dec. 5, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile ferroelectric memory device and a method for operating a main bitline load controller thereof, which improve a sensing voltage margin of a main bitline.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off states. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 illustrates a hysteresis loop of a general ferroelectric memory. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory will be described with reference to the accompanying drawings.
FIG. 2 is a schematic diagram of a unit cell of a general nonvolatile ferroelectric memory device. As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and a second terminal is connected with the plate line P/L.
In case where the related art nonvolatile ferroelectric memory device includes a plurality of main bitlines and a plurality of sub bitlines connected to the main bitlines, a main bitline load controller is arranged near a sensing amplifier.
FIG. 3A illustrates a timing diagram of a write mode operation of the related art ferroelectric memory and FIG. 3B illustrates a timing diagram of a read mode operation of the related art ferroelectric memory.
During the write mode, an externally applied chip enable signal CSBpad is activated from the high state to the low state. At the same time, if a write enable signal WEBpad is applied from the high state to the low state, the write mode starts. Subsequently, if an address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from the low state to the high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at the high state. To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor. On the other hand, a low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described.
If an externally applied chip enable signal CSBpad is activated from the high state to the low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data Qs corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory. If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data Qns is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. In other words, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transited to an xe2x80x9cfxe2x80x9d state as shown in the hysteresis loop of FIG. 1. If the data is not destroyed, the xe2x80x9caxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value xe2x80x9c1xe2x80x9d is output in case that the data is destroyed while the logic value xe2x80x9c0xe2x80x9d is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the original data, the plate line becomes inactive from the high state to the low state in a state that the high signal is applied to the corresponding wordline. The aforementioned related art nonvolatile ferroelectric memory device has several problems.
Since the single main bitline load controller is arranged near the sensing amplifier, the main bitline sensing voltage is reduced by the resistance component of the main bitline. For this reason, a problem arises in that the entire sensing margin is reduced.
Accordingly, the present invention is directed to a nonvolatile ferroelectric memory device and a method for operating a main bitline load controller thereof that substantially obviate one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a nonvolatile ferroelectric memory device and a method for operating a main bitline load controller thereof that improve a sensing voltage margin of a main bitline.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a nonvolatile ferroelectric memory device according to an embodiment of the invention includes a plurality of cell array blocks provided with a plurality of sub cell array blocks having a plurality of unit cells, a plurality of main bitlines arranged in the sub cell array blocks in one direction for each unit of column, a plurality of sub bitlines connected with the unit cells to induce a voltage in the unit cells and arranged along the main bitlines, a plurality of main bitline load controllers respectively arranged at least in the uppermost area and the lowest area of the sub cell array blocks so that one end of each of the main bitline load controllers is connected with the main bitline and the other end of each of the main bitline load controllers is connected with a high level applying terminal, a sensing amplifier block including a plurality of sensing amplifiers commonly used in the cell array blocks and amplifying signals of the main bitlines, and switching transistors arranged one per sub bitline to sense data values of the unit cells using current by varying a current flow depending on the voltage induced in the sub bitline and a voltage transferred to the main bitlines.
In another aspect of the present invention, a method for operating a main bitline load controller of a nonvolatile ferroelectric memory device, includes the steps of: preparing the nonvolatile ferroelectric memory device which includes a plurality of sub cell array blocks having a plurality of unit cells, and a plurality of cell array blocks provided with main bitline load controllers driven by a main bitline load control signal at the uppermost and lowest areas of the sub cell array blocks; selecting a cell driving area; and turning on at least one main bitline load controller nearest to the sub cell array block corresponding to the selected cell driving area.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.